Synchronous reference frame (SRF) PLL
TN103Table of Contents
This note provides insights into the operating principle of a synchronous reference frame PLL (SRF PLL), also known as DQ-type PLL. An implementation of an SRF PLL is found in the ACG SDK as the DQ-type PLL block and in the CPP SDK in the API folder of the template project. For a different type of PLL, please refer to the page on the SOGI PLL. Also, note that this page will focus on the three-phase implementation of the PLL. Single phase PLL are discussed in Fictive axis emulation (FAE) for single-phase inverter. Finally, typical use cases for DQ-type PLLs are listed at the end of the page.
What is a synchronous reference frame PLL?
Most of today’s grid-tied power converters aim to control active and reactive power flow. Accurate phase tracking systems are then required to synchronize the controlled currents or voltages with the utility grid voltages. Many grid-synchronization techniques exist and an extensive review of the possible implementations can be found in [1].
A synchronous reference frame PLL is a basic type of phase-locked loop based on the Park transform. In a nutshell, the SRF PLL is built using a Park transformation that acts as a phase detector, a low-pass filter (LPF) usually in the form of a PI regulator, and a voltage-controlled oscillator (VCO) typically made from an integrator [2]. The objective of this PLL is then to minimize either the direct or quadrature axis reference voltage. This will then ensure that the phase angle of the rotating reference frame of the park transformation matches the phase angle of the utility grid voltage vector [3].
The general principle of an SRF PLL is given below:
SRF PLL implementation
As mentioned, the idea behind the synchronous reference frame PLL is to detect the phase angle by synchronizing the rotating frame reference of the PLL to the utility grid voltages. The structure proposed for the SRF PLL is shown below. The park transform and the PI controller are very classic. The integrator is based on the forward Euler method, following the corresponding difference equation: \(y_n = y_{n-1} + h f(t_n, y_n)\), with the only specificity being that the output is wrapped between \([0; 2\pi[\).
Regarding the dynamic performances of the SRF PLL, it is difficult to get both fast-tracking and good filtering characteristics. Indeed, as stated in [2], a trade-off between these two characteristics is necessary when tuning the control loop parameters. For a PLL with better dynamic performance, one can look into the page: SOGI PLL.
Academic references
[1] M. Boyra and J. Thomas, “A review on synchronization methods for grid-connected three-phase VSC under unbalanced and distorted conditions,” in Proc. EPE Conf., Birmingham, 2011.
[2] S.-K. Chung, “A phase tracking system for three-phase utility interface inverters,” IEEE Transactions on
Power Electronics, vol. 15, no. 3, May 2000.
[3] L. Arruda and B. Silva, S.M.and Cardoso Filho, “PLL structures for utility connected systems,” in 2001 IEEE
Industry Applications Society 36th Annual Meeting (IAS’01), Chicago, USA, Sep./Oct. 30–4, 2001
Use case examples
As introduced above, phase-locked loops are used in most of today’s grid-tied power converters. Here are a few examples of such converters:
