AXI4-Stream IPs from Xilinx
This page presents some useful Xilinx IP cores for Vivado. These IPs use the widely used AXI4-Stream protocol to easily exchange data with other Xilinx IPs or with user-made algorithms developed using High-Level Synthesis (HLS) design tools such as Model Composer or Vitis HLS. For more detailed information on the AXI4-Stream interconnect protocol, please refer…