The operation of a grid-tied power converter (such as the 3-phases PV inverter) requires that the control software implements a grid synchronization technique. One well-known approach consists in using a three-phase PLL to project the AC grid quantities into a synchronous rotating reference frame. The PLL algorithm is usually executed on the CPU of the…
Control algorithms for power electronics converters often rely on PI controllers executed on the CPU of the controller. That’s the technique used in most of the application notes on this knowledge. However, in some situations, it could be desired to run the control loop on an FPGA (e.g. to offload the CPU, or achieve much…
This technical note presents an FPGA-based Direct Torque Control (DTC) of a PMSM motor using Vivado HLS, coupled with the possibility to customize the FPGA firmware of a B-Box. This approach increases the responsiveness of the DTC implementation presented in AN004 by porting part of the control logic to the FPGA. Xilinx Vivado High-Level Synthesis (HLS) is…
The SFP ports on imperix controllers are typically used for interconnecting devices in a RealSync network. However, when customizing the FPGA firmware, imperix designed the system to allow these SFP ports to be repurposed for other communication protocols. Aurora 8B/10B or Aurora 64B/66B can be used to communicate with hardware-in-the-loop (HIL) simulators that support the…
The Sandbox Input from FPGA (SBI) block reads the value of the SBI registers in the FPGA. It is used to transfer data from user-made code from within the FPGA to the CPU. Information on FPGA edition is available on: Editing the FPGA firmware (sandbox) (PN116) Usage examples of the SBI block are available on:…
This technical note provides an example of how a fast hysteresis current controller can be implemented, leveraging the possibility of editing the FPGA firmware for rapid control prototyping applications. This example implements the direct current control of a three-phase passive load. It relies on manually-generated VHDL code. The automated generation of VHDL code is presented…
This note provides step-by-step guidance to create a Xilinx Vivado project, add customized logic, generate a bitstream, and load it into the B-Box/B-Board. The required software and sources files are: Vivado HL Design Suite (available for free as the WebPACK edition) Sandbox sources Software resources Installing Vivado SDK A Xilinx account is needed to download…
This page provides step-by-step guidance to install Xilinx Vivado Design Suite, the tools used to program the FPGA of imperix controllers.
This technical note shows how the implementation of an FPGA-based hysteresis controller can be conducted, starting from the modeling stage, following with automated VHDL code generation with HDL Coder, and finishing with its validation in simulation. As an application example, this note uses the hysteresis current control already shown in TN120. HDL Coder is a MATLAB…
The FPGA sandbox PWM block allows driving the PWM output from a user-made modulator from within the FPGA. Information on FPGA edition is available on Editing the FPGA firmware (sandbox) (PN116) Usage examples of the FPGA sandbox PWM block are available on: FPGA-based direct torque control using Vivado HLS (TN133) FPGA-based hysteresis current control (TN120) Because…
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