Recent advances in wide bandgap semiconductors have made Silicon Carbide (SiC) and Gallium Nitride (GaN) increasingly popular and now widely adopted in low- to mid-power applications. Simultaneously, engineers are also observing – and expressing – increasingly demanding needs regarding the hardware around the power switches. This trend pushes for performance improvements in gate drivers, sensors, auxiliaries, but also in the generation of PWM signals and the overall digital control system. Indeed, when everything happens 5-10x faster (or more) than with silicon, the whole control stage must be able to keep up!

It is not straightforward to quickly identify the essential specifications when it comes to driving wide bandgap semiconductors. Also, some challenges may remain incompletely addressed by existing digital controllers. This article gives some insight into five specific points: 1) PWM resolution, 2) Timing accuracy of PWM gating signals, 3) Closed-loop control rate, 4) System-level flexibility and scalability, and 5) Device protection.

1) PWM resolution

PWM resolution can be defined as the smallest increment of pulse width that can be applied to a given PWM signal. This parameter directly affects the accuracy and noise performance of a regulated quantity, similarly to A/D conversion resolution.

The faster the switching frequency, the lower must be the PWM resolution for constant performance. Typically, achieving a relative resolution of 10bits (i.e., 0.1%) with a switching frequency of 2.5kHz requires an absolute PWM resolution of 400ns. Most modern digital modulators easily exceed this performance. However, achieving the same relative resolution at 250kHz requires an absolute resolution as low at 4ns, which is already an outstanding level of performance!

The necessity to achieve such a resolution may be questionable, depending on the application. Nevertheless, it may be essential to have these figures in mind when evaluating a pulse-width modulation system. For instance, the same resolution of 4ns only allows achieving a relative resolution of 1% (6.5bits) at 2.5MHz.

Title (h4)

Title (h5)

• line 1
• line 2
• line 3

2) Timing accuracy of PWM gating signals

The overall timing accuracy of PWM signals can be defined as the accuracy – in time – of every signal edge with respect to related signals. It may also be designated as the total timing uncertainty. PWM resolution aside, it is notably influenced by jitter and skew along the whole signal chain from the modulator to the gate of the power semiconductors.

Total jitter is often negligible. However, skew depends on asymmetries between related signal paths, which may be more significant. They may be due to part-to-part variations, or characteristics of the logic circuits themselves. Skew values ranging from few nanoseconds up to tens of nanoseconds are not uncommon.

When it comes to driving power semiconductors, the faster the devices, the more accurate the driving signals must be. This is mostly constrained by the need to minimize the dead time, which is a well-known source of harmonic distortion (and to a lesser extent, losses). Furthermore, paralleling power semiconductors also requires very accurate driving signals.

As an example, the driving of an imperix PEB8024 power module with a B-Box RCP involves the following timing uncertainties:

In this example, the total estimated worst-case skew is about 83ns, which typically allows the dead-time to be configured as low as 90-100ns. This is essential in order to minimize distortion in applications with a high switching frequency. Importantly, the digital controller here contributes to only one-sixth of the minimum dead time, which grants a large headroom for more demanding scenarios. This objective is behind the introduction on the B-Box RCP of electrical PWM outputs, which offer superior performance over optical outputs, with a total timing uncertainly as small as 2.3ns!

3) Closed-loop control rate

In power electronics, the main constraint in terms of closed-loop control bandwidth is often set by the equivalent actuator delays, which depend on the sampling and switching frequencies. With higher switching frequencies, new harmonic performance levels can be reached. However, in order to fully benefit from the performance increase, other delays must also be kept under control, such as measurement and processing delays, as well as data transmission latencies.

Historically, closed-loop control frequencies above hundreds of kHz were only achievable using special FPGA-based systems and highly customized control implementations. Nowadays, modern Systems on Chip (SoC) – such as within the B-Box RCP – can also offer minimal latencies, but with the additional benefit of simultaneously offering a more straightforward control implementation and debugging. Processor-based systems are indeed much easier to integrate into semi- of fully-automated code generation toolchains such as, for instance, using Matlab Simulink.

The figure below shows a typical allocation of data transfer delays achieved with the B-Box RCP at 100kHz. The available CPU processing time is about 7.8µs, i.e., 78% of the total PWM period. Other sampling scenarios are obviously possible.

4) System-level flexibility and scalability

Modern power electronic systems tend to be increasingly modularized. Notably, the limited ratings of today’s wide bandgap devices encourage their use in a modular fashion in order to extend the system-level power ratings. This may take the form of simple paralleling or more sophisticated approaches. Anyhow, multiple devices or subsystems are used together in order to gain in scalability. This notably calls for the capability to acquire data from multiple sensors as well as to distribute control outputs among several devices, units, or even locations!

Such flexibility must cope with the design uncertainties that unavoidably remain during the development phase, but also as to enable future system extensions and upgrades or simply to foster re-usability between projects. Unfortunately, the traditional design approach used by most industrial controllers, based on monolithic circuit boards, are unable to provide such flexibility. The modularization of the power stage also requires some sort of modularization of the control stage too!

Imperix controllers feature relatively modest I/O capabilities per unit, but distinguish by their excellent performance in networked configurations, thanks to a high-end optical fiber interconnect. This offers tremendous scalability – ranging up to thousands of inputs and outputs – guaranteeing that no system is ever too large or complex. Furthermore, because all related data transfers are achieved with an extremely low latency, users are guaranteed that the overall system can be operated in a transparent fashion, regardless of this unusual structure. (Typical performance results indeed showcase sub-microsecond latencies for hundreds of measurements and PWM parameters.)

5) Device protection

The primary benefit of the increased switching frequencies enabled by SiC devices is the resulting possible reduction in size and weight of their associated passive elements. Transformers, inductors, and filters can indeed be attractively downsized, which also results in smaller time constants and larger current rise rates. Furthermore, as the wide bandgap technology is still evolving, the ruggedness of the devices has not yet reached the level of their silicon counterparts, notably regarding short-circuit withstand times, which remain relatively limited.

Altogether, this imposes that protective measures can act particularly fast. This is uneasy for device-level protection because desaturation detection must accurately respond to the fault in a particularly noisy environment (high dv/dt and di/dt). At the system level, the challenges are similar, once again due to the notably faster current dynamics.

In this context, it is always good to be able to rely on rock-solid protective mechanisms, especially during the research and development phase. This is notably essential in order to be able to push and observe the capabilities of SiC devices close to their limits, without endangering their integrity. This is the main reason why the imperix B-Box RCP embeds software-independent safety mechanisms, which can respond as fast as 1.4us between the detection of the overvalue and the blocking of all PWM signals.

References

[1] M. Hagiwara, H. Akagi, “Control and Experiment of Pulsewidth-Modulated Modular Multilevel Converters,” in IEEE Transactions on Power Electronics, Vol.24, July 2009.
[2] P. Münch, D. Görges, M. Izák and S. Liu, “Integrated current control, energy control and energy balancing of Modular Converters,” in Proc. IECON Conference, Phoenix, 2010.

The post SiC-related challenges for digital control systems appeared first on imperix.

Minimum requirements:

• Imperix ACG SDK 3.6.0.0 or newer.
• MATLAB Simulink R2017b or newer.
• Plexim PLECS VIEWER 4.4.2 or newer (free).

Principles of operation

The control implementation is largely inspired from [1], which is a key reference regarding the control of MMC with carrier-based modulation. Two minor differences are however present – and somewhat recommended – between [1] and this example:

• The arm-level vertical energy balancing is not achieved indirectly through the so-called averaging control, but instead is done explicitly by an associated controller, acting on the AC-side converter reference. This approach offers a better decoupling of the cell- and arm-level balancing mechanisms and allows to improve the cell-level dynamics.
  On the other hand, the corresponding energy exchanges remain related to the AC side of each phase leg, which means that they may lead to slight asymmetries in the grid currents during the balancing transients. Alternative approaches exist, typically altering the circulating currents in such a way that the total DC is unchanged. A recommended reference on this topic is [2].
• The DC-side dynamics are improved by feed-forwarding the AC-side active power into the DC-side current control. This facilitates the control of the total embedded energy, i.e. overall average capacitor voltage. More subtle approaches can be used, which are typically relevant in case of operation under unbalanced grid conditions, or single-phase systems.

References

[1] M. Hagiwara, H. Akagi, “Control and Experiment of Pulsewidth-Modulated Modular Multilevel Converters,” in IEEE Transactions on Power Electronics, Vol.24, July 2009.

[2] P. Münch, D. Görges, M. Izák and S. Liu, “Integrated current control, energy control and energy balancing of Modular Converters,” in Proc. IECON Conference, Phoenix, 2010.

The post DC/AC Modular Multilevel Converter (MMC) appeared first on imperix.

At imperix, we strongly believe that accurate simulation results help our customers develop efficient control algorithm, and eventually speed up the transition to real-world experiments. But how do we make sure that our models actually represent what happens on a real controller?

I’m going to briefly show you a particular example of how we have validated our carrier-based modulator models on Simulink.

The process is quite simple and straightforward: we capture the PWM signals from a simulation run and compare them with those measured on a B-Board PRO that runs the exact same model. The real PWM signals are measured using a logic analyzer and the data is transferred to the PC to be analyzed.

To make sure that the test is as generic as possible, we use randomly generated duty-cycle and phase values, stored in a lookup table.

Finally, we run a MATLAB script that compares the PWM signals, using a synchronization pulse to align the simulation and experimental time axes.

The tolerated error between simulation and experimental results takes into account the PWM resolution of the B-Board PRO (4 ns) and the time resolution of the logic analyzer (2.5 ns). In total, an error of 13 ns on a pulse width is tolerated. The test is then marked as “PASS” if none of the simulated PWM pulses differ from the measured pulses by more than 13 ns.

The post Validation of our simulation models appeared first on imperix.

The timing info graph is a new BB Control feature provided by the SDK version 3.6 (currently in development). The beta version can be found on our download page. It displays the following information:

• CLOCK_0: Shows the clock used as the main time base. PWM modulators are typically also connected to this clock.
• SAMPLING: Shows the sampling instants relative to CLOCK_0. It this screenshot the sampling is performed in the middle of the CLOCK_0 period, which corresponds to the middle of the switching period of the PWM connected to this clock.
• ACQ: This delay is the time necessary to acquire and converter the analog data, it is specific the ADC chip
• READ: Is the time it takes for the data to be transferred from the peripherals (in the FPGA) to the CPU memory. Typical data are ADC conversion results, GPI values, etc.
• CPU PROCESSING: Shows the time spent in the interrupt service routine. This delay is separated into two parts: the control processing and post processing. The former is the delay to execute the control algorithm and the latter is the operations that are not directly part of the control algorithm such as datalogging, CAN communication, etc.
• WRITE: The time it takes to write data back to the FPGA. The data typically are duty-cycles, GPO values, etc.
• CYCLE DELAY: The cycle delay is the sum of all the delays involved in the control dynamics.

I am aware that this is a lot of information and maybe not all of them are useful to you. But if you need to keep only the most important one, it would be the cycle delay. The reason is that, as mentioned earlier, this is the delay that will define the dynamic of your system. This delay can even be taken into account in simulation (with the ACG SDK) to accurately model the time at which the PWM parameters are actually updated, allowing to adjust the control parameters accordingly (Kp and Ki for instance).

Note that the WRITE operation is executed right after the control task. This allows to reduce the cycle delay and to completely eliminate the computation delays variations due to the datalogging or other post control processes.

The post The new timing info graph appeared first on imperix.

• liste
• fd
• fdf
• df
• df

• liste 2
• texte
• texte

The post Vestibulum efficitur vel felis appeared first on imperix.

How to stack B-Boxes?

Using multiple imperix power controllers in a networked configuration is actually quite simple!

1. Connecting the units using optical fiber

Using optical fibers, the units must be connected in a pyramidal network as illustrated in the image below. The master B-Box is sitting on top of the network and is the only unit without an UP connection.

2. Addressing the I/Os

In a multi-device setup, the B-Box LCD screen indicates the device ID. To use a carrier-based modulator (CB-PWM) for instance, you simply have to specify the device ID and the PWM channel.

What are the application

The clock synchronization ensures that there is absolutely no drift between the PWM outputs, they act as if the B-Boxes & B-Boards were a single unit! Moreover, the performance of the high-speed fiber (5Gbps) coupled with our fully custom protocol brings extremely low latencies, enabling the possibility to connect a larger number of devices and still being able to keep exchange rates in the hundreds of kHz range. Here are some application scenarios:

Scenario 1: a large number of I/Os is required, for instance a MMC using 24 full bridge power modules such as the one proposed in our bundles.

Scenario 2: industrial-grade converters based on the B-Board PRO embeddable controller with a centralized control

Scenario 3: fully distributed solution, each power module has it’s own B-Board controller and all signal exchanges are performed through the RealSync network

What’s next?

For now only the I/O extension mode is supported where only one CPU (inside the master unit) is running. But we are currently working on a fully-distributed control mode in which it will be possible to have multiple CPU running (therefor multiple control code) in the same network! In this mode a master unit will be able to access the I/Os of the units below, as such it will be possible to implement sub-loops….. blablabla

H2 title

For now only the I/O extension mode is supported where only one CPU

H3 title

For now only the I/O extension mode is supported where only one CPU

H4 title

For now only the I/O extension mode is supported where only one CPU

H5 title

H6 title

The post Stacking B-Boxes for more I/Os appeared first on imperix.